There are many ways to solve the EMI problem. Modern EMI suppression methods include the use of EMI suppression coatings, the selection of appropriate EMI suppression parts and EMI simulation design. This article starts from the most basic PCB layout and discusses the role and design techniques of PCB layered stacking in controlling EMI radiation.
Reasonable placement of capacitors with appropriate capacity near the power pins of the IC can make the output voltage of the IC jump faster. However, the problem does not end there. Due to the finite frequency response of capacitors, this prevents them from generating the harmonic power needed to drive the IC output cleanly over the full frequency band. In addition to this, transient voltages developed on the power busbars create a voltage drop across the inductance of the decoupling path, and these transients are the main source of common-mode EMI interference. How should we solve these problems?
In the case of an IC on our board, the power plane around the IC can be thought of as a good high-frequency capacitor that harvests the energy leaked by the discrete capacitors that provide high-frequency energy for a clean output. In addition, the inductance of a good power supply layer should be small, so that the transient signal synthesized by the inductance is also small, thereby reducing common mode EMI.
Of course, the connection from the power plane to the IC power pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster, it is best to directly connect to the pad where the IC power pin is located, which is discussed separately.
To control common-mode EMI, the power plane must be a reasonably well-designed pair of power planes to facilitate decoupling and have sufficiently low inductance. The great power plane depends on the layering of the power supply, the materials between the layers, and the operating frequency (that is, a function of the IC’s rise time). Typically, the power layer spacing is 6mil, and the interlayer is FR4 material, so the equivalent capacitance per square inch of the power layer is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.
There are not many devices with rise times of 100 to 300ps, but according to the current IC development speed, devices with rise times in the range of 100 to 300ps will occupy a high proportion. For circuits with rise times of 100 to 300ps, 3mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use a layered technique with a layer spacing of less than 1 mil and to replace the FR4 dielectric material with a material with a very high dielectric constant. Now, ceramics and ceramics can meet the design requirements of 100 to 300ps rise time circuits.
Although new materials and methods may be adopted in the future, for common today 1 to 3ns rise time circuits, 3 to 6mil interlayer spacing, and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and to keep transients low enough, that is to say, common mode EMI can be reduced very low. The PCB layered stackup design examples given in this article will assume a layer spacing of 3 to 6 mils.
From the point of view of signal routing, a good layering strategy should be to put all signal routing on one or several layers, and these layers are next to the power plane or ground plane. For power, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible, which is what we call the “layering” strategy.
What stacking strategies help shield and suppress EMI? The following layered stacking scenarios assume that the supply current flows on a single layer, with single or multiple voltages distributed on different parts of the same layer. The case of multiple power planes is discussed later.
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