There are several potential problems in the design of the 4 layer PCB.
First of all, the traditional four-layer plate with a thickness of 62miL is too large even if the signal layer is in the outer layer and the power source layer and the ground layer are inside.
If cost requirements are the first consideration, consider the following two alternatives to the traditional 4 layer.
Both solutions improve EMI suppression performance, but only in cases where the on-board component density is low enough and there is sufficient area around the component to place the required power copper coating.
The first is the preferred solution. The outer layer of THE PCB is stratified, and the middle two layers are signal/power layer.
The power supply on the signal layer is wired with a wide line, which makes the path impedance of the power supply current low, as well as the impedance of the signal microstrip path.
From an EMI control point of view, this is the best 4-layer PCB structure available.
In the second scheme, the outer layer is the power supply and the ground, and the middle two layers are the walking signals.
Compared with the traditional 4-laminates, the improvement of the scheme is smaller, and the inter-laminates impedance is as poor as the traditional 4-laminates.
If the routing impedance is to be controlled, the stack scheme above should be very careful to arrange the wiring under the power supply and the grounding copper island.
In addition, the power supply or copper-laying islands in the formation should be interconnected as far as possible to ensure DC and low frequency connectivity.
If the density of components on a 4-ply board is high, it is better to use a 6-ply board.
However, some lamination schemes in the design of 6-ply plates are not good enough to shield the electromagnetic field and have little effect on reducing the transient signal of the power bus.
Two examples are discussed below.
In the first case, the power supply and the ground were placed on the second and fifth layers respectively. Due to the high resistance of copper coating on the power supply, it was very unfavorable to control common mode EMI radiation.
However, from the point of view of signal impedance control, this method is quite correct.
In the second case, the power supply and ground are placed on the third and fourth layers respectively. This design solves the problem of copper coating impedance of the power supply. Due to the poor electromagnetic shielding performance of the first layer and the sixth layer, the EMI of differential mode is increased.
This design can solve the differential EMI problem if the number of signal lines on the two outer layers is minimal and the line length is short (shorter than 1/20 of the wavelength of the highest harmonic wave of the signal).
The non-component and non-wire area on the outer layer is filled with copper and grounded (1/20 wavelength interval), which is particularly good for the suppression of DIFFERENTIAL mode EMI.
As mentioned above, the copper-laying area should be connected with multiple points of the internal strata.
The general high performance 6-plate design generally covers the 1st and 6th layers as strata, and the 3rd and 4th layers as power supply and ground.
EMI suppression ability is excellent because there are two middle layers of double microstrip signal lines between the power layer and the ground layer.
The disadvantage of this design is that there are only two layers of wiring.
As described earlier, the same stack can be achieved with a traditional 6-ply plate if the outer thread is short and copper is laid over the non-thread area.
The other six-ply board layout is signal, ground, signal, power, ground, signal, which enables the environment required for advanced signal integrity design.
The signal layer is adjacent to the ground layer, and the power layer is paired with the ground layer.
Obviously, the downside is the stack imbalance of the layers.
This usually leads to manufacturing problems.
The solution is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to the power layer or the connecting layer after copper filling, the plate can be regarded as a structurally balanced circuit board loosely.
The copper filling area must be connected to power supply or ground.
The distance between the connecting holes is still 1/20 wavelength, not necessarily everywhere, but ideally it should be connected.
Because the insulation between the boards is very thin, the impedance between the 10 or 12 board layers is very low, and as long as the layering and stacking are not problematic, excellent signal integrity is completely expected.
It is more difficult to manufacture 12-layer plates according to the thickness of 62mil, and there are not many manufacturers that can manufacture 12-layer plates.
Since there is always an insulating layer between the signal layer and the loop layer, the scheme of allocating the middle 6 layers to run the signal line in the 10 layer design is not optimal.
In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.
This design provides a good path for signal current and its loop current.
The appropriate routing strategy is for layer 1 to go in the X direction, layer 3 to go in the Y direction, layer 4 to go in the X direction, and so on.
Visually, the first and third layers are a pair of layered combinations, the fourth and seventh layers are a pair of layered combinations, and the eighth and tenth layers are the last pair of layered combinations.
When it is necessary to change the direction of the line, the signal line on the first layer should change its direction by passing through the hole to the third layer.
In practice, this may not always be possible, but as a design concept it should be followed.
Similarly, when the routing direction of the signal changes, layers 8 and 10 or 4 to 7 should be traversed through the hole.
This wiring ensures the tightest coupling between the forward path and the loop of the signal.
For example, if the signal is wired on the first layer and the circuit is wired on the second layer and only on the second layer, then the signal on the first layer, even if it passes through the “hole” to the third layer, will still loop on the second layer, thus maintaining the characteristics of low inductance, large capacitance and good electromagnetic shielding energy.
What if the actual wiring is different?
For example, when the signal line on the first layer passes through the hole to the 10th layer, the loop signal has to find the ground plane from the ninth layer, and the loop current has to find the nearest ground through hole (such as the grounding pin of resistance or capacitor and other components).
If you happen to have a hole like this nearby, you’re lucky.
If such a close hole is not available, the inductance will become larger, the capacitance will decrease, and the EMI will increase.
When the signal line must leave the current pair of wiring layers to other wiring layers through the through-hole, the grounding through-hole should be placed close to the through-hole so that the loop signal can return to the appropriate grounding layer smoothly.
For layer-4 and layer-7 combinations, the signal loop will return from the power layer or the ground layer (i.e., layer 5 or 6), because the capacitive coupling between the power layer and ground layer is good and the signal is easy to transmit.
If the same voltage source of two power layers need to output a large current, the circuit board should be distributed into two groups of power layer and contact layer.
In this case, an insulating layer is placed between each pair of power layer and the connecting layer.
This results in two pairs of power busbars with equal impedances of the expected bisected current.
If the stack of power layers causes unequal impedances, the shunt will be uneven, the transient voltage will be much higher, and the EMI will increase dramatically.
If there are multiple voltages of different values on the circuit board, multiple power layers will be required, bearing in mind that each pair of power layers and bonding layers will be created for the different power sources.
In both cases, the manufacturer’s requirements for a balanced structure are in mind when determining the location of the paired power layer and bonding layer on the circuit board.
Since most engineers design 62mi-thickness printed circuit boards with no blind or buried holes, the discussion of layering and stacking of circuit boards in this article is limited to that.
For boards with very different thickness, the recommended layering scheme may not be ideal.
In addition, the layering method in this paper is not applicable for the circuit board with blind hole or buried hole.
The thickness, through-hole process and the number of layers of the circuit board are not the key to solve the problem in the circuit board design. Excellent layering and stacking are the key to ensure the bypass and decoupling of the power bus, minimize the transient voltage of the power layer or layer, and shield the signal and the electromagnetic field of the power source.
Ideally, there should be an insulating layer between the signal routing layer and the loop connecting layer, and the matched layer spacing (or more than one pair) should be as small as possible.
According to these basic concepts and principles, the circuit board can always meet the design requirements.
Now that IC’s ascent time is short and will be even shorter, the techniques discussed in this article are essential to solve the EMI shielding problem.
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