There are many ways to solve the EMI problem. Modern EMI suppression methods include: EMI suppression coating, appropriate EMI suppression parts and EMI simulation design. Starting from the most basic PCB board, this paper discusses the role of PCB layering and stacking in EMI radiation control and design techniques.
The jump of IC output voltage can be made faster if the capacitance of appropriate capacity is placed reasonably near the IC’s power supply pin.
However, the problem does not end there.
Due to the capacitance’s finite frequency response, this prevents the capacitor from generating the harmonic power needed to drive the IC output cleanly over the full frequency band.
In addition, the transient voltages formed on the power bus will form a voltage drop at both ends of the inductance of the decoupling path, and these transient voltages are the main common mode EMI interference sources.
How should we solve these problems?
In the case of our IC on the circuit board, the power layer around the IC can be regarded as a good high frequency capacitor, which can collect the leakage of the discrete capacitor that provides the high frequency energy for the clean output.
In addition, the inductance of the excellent power layer should be small, so the transient signal synthesized by the inductance is also small, thus reducing the common mode EMI.
Of course, the connection from the power layer to the IC power pin must be as short as possible, because the digital signal is rising faster and faster, it is better to connect directly to the solder pad where the IC power pin resides, which is another discussion.
In order to control common-mode EMI, the power layer must be a pair of reasonably well designed power layers to facilitate decoupling and have sufficiently low inductance.
One might ask, how good is good?
The answer to the question depends on the layering of the power supply, the materials between the layers, and the working frequency (i.e. the function of IC rise time).
Typically, the power layer is spaced at 6mil and the sandwich is made of FR4 material, so the equivalent power capacity per square inch of the power layer is approximately 75pF.
Obviously, the smaller the layer spacing is, the greater the capacitance will be.
There are not many devices with ascent times of 100 to 300ps, but at the current rate of IC development, a high percentage of devices with ascent times of 100 to 300ps will be present.
For circuits with 100 to 300ps rise times, 3mil layer spacing is no longer applicable for most applications.
At that time, it was necessary to use layering techniques with intervals of less than 1mil and replace FR4 dielectric materials with materials with high dielectric constants.
Now, ceramics and ceramic plastics can meet the design requirements of 100 to 300ps rise time circuits.
Although new materials and methods may be used in the future, for today’s common 1 to 3ns rise time circuits, 3 to 6mil layer spacing and FR4 dielectric materials, high harmonics are usually sufficiently processed and transient signals are sufficiently low, that is, common mode EMI can be reduced very low.
An example of a layered and stacked PCB design presented in this paper will assume a layer spacing of 3 to 6mil.
From the point of view of signal routing, a good layering strategy should be to line all signals in one or several layers, which are adjacent to the power layer or ground layer.
For the power supply, a good stratification strategy should be one in which the power supply layer is adjacent to the ground layer and the distance between the power supply layer and the ground layer is as small as possible, which is the “stratification” strategy we refer to.
What stacking strategy helps mask and suppress EMI?
The following layered stack scenario assumes that the supply current flows on a single layer, with single or multiple voltages distributed over different parts of the same layer.
The multi-layer scenario is discussed later.
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