Low-cost, high-density interconnect (HDI) organic substrates are the most important conditions for implementing the system-level encapsulation (SOP) technique. The crux of the matter is that ultra-precision wiring must be etched into organic plates such as FR4 at very small intervals. NEMI, SIA, IPC and ITRI research institute report that in future chip design process, base material suppliers must have the process to produce low cost fine line.

At present, the integration level shows an increasingly high trend, many companies have started SOC technology, but SOC cannot solve all the problems of system integration, so in the packaging research Center (PRC) and many other research institutions, the system packaging (SOP or SIP) as a supplement to SOC solutions. The integration of SOP and SOC can meet the requirements of the new generation system design.

The SOP technologies studied by PRC include the integration of passive components such as resistors, capacitors, inductors, optical devices, and RF components using MEMS processes, as well as low-cost cooling devices, mixed signal design and testing, related design tools, and low-cost flip chip installation processes without the use of bottom-filling materials. Of course, the BASIS of THE SOP technology is the reliable high-density interconnection of materials, processes, and materials.

High density cabling technical requirements

At present, the processing technology of printed wiring board (PWB) lags behind the development of electronic device packaging seriously. The key to solve this problem lies in the laser etching technology of wiring and pore forming process. Line width and spacing from 62.5 microns to 25 microns, the processing technology is very different.

With the efforts of groups such as ITRI and NEMI, the 75 to 100 microns wire-width and spacing processes are increasingly used in large-area PWBS, resulting in significant breakthroughs in PWB wire forming technology.

At present, the HDI substrate process has been used to achieve 30 to 40 microns line width and between lines and 75 to 100 microns microporous. PRC is committed to developing processing technologies up to 25 microns to meet the requirements of precision wire routing and wire spacing for large area organic sheets. The goal is to develop 15 to 25 microns superdense lines and 25 to 50 microns microporous processes that will eventually lead to 6 to 10 microns lines and 10 to 15 microns perforations.

MCM technology multi-chip module (MCM) technology can meet the requirements of SOP, but the cost is too high.

McM-d (deposited MCM) has a high wiring density and can be installed with passive devices and waveguides, but it is expensive to produce.

McM-c (ceramic MCM) also meets the requirements of SOP and can be integrated with RF structure. However, it is difficult to promote its application due to cost.

Low cost, easy to process, suitable for large plate processing, so it can meet the requirements of SOP for price and performance. The PWB manufacturing industry usually refers to wire widths of less than 100 microns as “fine lines”. Now the line widths can be as small as 50 to 35 microns. As a result, the concept of fine lines, ultra-fine lines and ultra-fine lines and line spacing is not clearly defined. The very fine line discussed in this article refers to a line width of less than 50 microns that meets the needs of the industry today and for some time to come. Ultrafine is defined as a line of less than 15 microns wide enough to be flipped inside a precision spacing array in the next few years.

PRC is developing next generation packages and other applications based on low-cost panels to meet the needs of SOP/SLIM.

The two key factors that affect “ultra-fine” and “ultra-fine” fine and interwire machining are:

1. Print high resolution photoresist diagrams on the substrate through design or mask tools;

2. Very fine copper wire at low cost.

Of the two factors, photoresist imaging technology is more critical. It is difficult to print the target characteristic geometry on a low-cost substrate. As you can see from the semiconductor manufacturing process, the PWB must be made from an inexpensive photoresist material.

Another factor to note is the substrate.

Silicon wafers and other semiconductor substrates have extremely smooth and flat surfaces, while low-cost organic plates such as FR4 are hard and rough, which must be taken into account in the development of new technologies and processes. At present, a series of experiments are being carried out to explore the feasibility of machining fine lines on rigid organic plates. The evaluation was completed with two dry films of different thickness and two widely used liquid photoresists.

High TgFR4 plates (copper-free, single-sided and double-sided) were used in the process evaluation. In the experiment, an electrode copper-free plated insulating layer is formed by epoxy-base dry film between multi-layer plates FR4. The surface of the plate configured in this way is flat and smooth compared with the basic FR4 plate. All photoresist materials are compatible with water-soluble processing processes. The length of the test plate is 300 mm. Two liquid photoresists are deposited by rotating coating or crescent coating.

DuPont smvl-100 vacuum laminate the dry film photoresist material C1 (15mm thick) and C2(37.5mm thick) are laminated on the circuit board. In this study, a hard and soft light mask method was used. Experiments show that the dry film and liquid photoresist materials can be used to perfectly image the comb structure on copper-clad FR4 plates, with the line spacing of 0.635mm (line width/line spacing=312 microns) to 0.0508mm (line width/line spacing =20/30 microns or line width/line spacing =25/25 microns).

Comb structures with a spacing of 50 microns (25 microns line width and 25 microns line spacing) can be obtained by adding electroplating copper or reducing etching of copper foil. Photomicrographs of line width and line spacing of 15 microns copper wire on dry film photoresist show that the etching line is very straight, the photoresist adhesion force is acceptable, and the line edge is clear. The 10 microns line width and line spacing were etched successfully by using a low-cost liquid photoresist material.

Using a negative liquid photoresist material D, a line width of 7.5 microns can be etched. The experimental results show that with the improvement of processing technology and mask tools, it is possible to etch wires finer than 5 microns in the future. All materials and processes were compatible with HDI and existing technologies in the experimental evaluation of the pathway interconnection.

The combination of ultra-fine wire etching, metallization, and micro-through-hole interconnection processes can produce an Array of copper-per stud 35 microns in diameter, which forms the basis of a stacked micro-through-hole process on ultra-high-density ultra-HDI substrates. In addition, a series of microporous 35 microns diameters have been fabricated on thin photosensitive insulating films coated with FR4 plates. After 2,000 thermal cycles, the 50-micron micropore cross section shows good repeatability for typical PRC devices.

Conclusion:

PRC has already implemented 25 microns ultra-fine line and 15 microns ultra-fine line HDI technology, research under 7.5 microns and line spacing has been completed, and further 6 microns line and line spacing and 10 to 15 microns perforation processes will be developed over the next few years.

The next generation of chip technology requires line and line spacing to be below 10 microns, so that the ongoing SOP technology in the microelectronics industry can be truly successful.