In the PCB drawing device packaging, often meet with bonding pad size is not good to grasp the problem, because we refer to the information given is the size of the component itself, such as pin width, spacing, etc., but the size of the corresponding pad on the PCB board should is slightly larger than the size of the pin, or guarantee the reliability of the welding. The following will focus on the size of the welding plate specification.
In order to ensure the welding quality of SMT components (SMT), in the design of SMT printed board, in addition to the 3mm-8mm process edge should be set aside for the printed board, the welding plate graphics and dimensions of various components should be designed according to the relevant specifications, and the alignment of components and the spacing between adjacent components should be laid out. In our view, special attention should also be paid to the following points:
(1) Bare copper foil shall be used on printed boards where conductive graphics (such as interconnect wires, ground wires, mutual conductivity hole plates, etc.) and copper foil to be retained are located below the welding resistance film. In other words, it is never allowed to coat the metal coating whose melting point is lower than the welding temperature, such as tin-lead alloy, in order to avoid causing the crack or wrinkle of the welding film at the coating place, so as to ensure the welding and appearance quality of PCB board.
(2) When checking or invoking the graphic size information of the welding plate, it shall match the package shape, welding end, pin and other welding-related dimensions of the components it chooses. It is necessary to overcome the bad habit of copying or calling the graphic size of the welding plate in the data J or software library without analysis or comparison. When designing, checking or calling the graphic dimensions of the welding plate, you should also distinguish the components you choose, their codes (such as sheet resistance, capacitance) and the dimensions related to welding (such as SOIC,QFP, etc.).
(3) The welding reliability of surface mount components mainly depends on the length of the welding plate rather than the width.
(a) The length B of the pad is equal to the length T of the welding end (or pin), plus the extension length B1 of the inner side (pad) of the welding end (or pin), plus the extension length B2 of the outer side (pad) of the welding end (or pin), i.e., B=T+ b1 + b2. Among them, the length of B1 (about 0.05mm — 0.6mm) should not only be conducive to the welding spot that can form a good crescent shape contour when the solder melts, but also should avoid the welding phenomenon and take into account the component’s mounting deviation. The length of B2 (about 0.25mm — 1.5mm) is mainly appropriate to ensure that the welding spot can form the best crescent shape contour (for SOIC, QFP and other devices, the anti-peeling ability of the welding plate should also be taken into account)
(b) The width of the pad shall be equal to or slightly greater (or less) than the width of the end (or pin).
Schematic diagram of welding plate design of common mounting components, as shown below.
Pad length B=T+ b1 + b2
The inner spacing of the pads G= L-2T-2b1
Pad width A=W+K
The outer spacing of the pads D=G+2B.
L – component length (or the distance between the outside pins of the device);
W – Component width (or component pin width);
H – Component thickness (or component pin thickness);
B1 — Extension length of inner side (pad) of welding end (or pin);
B2 — The extension length of the outside (pad) of the end (or pin);
K – Correction of pad width.
Typical value of the extension length of welding plate for common components:
For rectangular sheet resistance and capacitance:
B1 = 0.05 mm, 0.10 mm, 0.15 mm, 0.20 mm, 0.30 mm one of them, the shorter the element length of the value should be smaller.
B2 = 0.25 mm, 0.35 mm, 0.5 mm, 0.60 mm, 0.90 mm, 1.00 mm, the thickness of the element of the thinner, the value should be smaller.
K=0mm, +/-0.10mm,0.20mm one of them, the narrower the component width, the smaller the value should be taken.
For SOIC and QFP devices of airfoil pins:
B1 = 0.30 mm, 0.40 mm, 0.50 mm, 0.60 mm one, device appearance outsiders, or adjacent pin center distance outsiders, take the value should be smaller.
B2 = 0.30 mm, 0.40 mm, 0.80 mm, 1.00 mm, 1.50 mm one of components supplied by appearance, have thrown some value.
K = 0 mm, 0.03 mm, 0.30 mm, 0.10 mm, 0.20 mm, the distance between adjacent pin center distance small person, take the value should be smaller.
B=1.50mm ~ 3mm, generally about 2mm is taken.
If the outer space allows, it can be as long as possible.
(4) No through holes (the distance between the through hole and the edge of the bonding pad shall be greater than 0.6mm) shall be allowed in the bonding pad and the bonding pad. If the bonding pad and the bonding pad are interconnected, a connection less than 1/2 of the width of the bonding pad, such as 0.3mm ~ 0.4mm, shall be connected to avoid various welding defects caused by solder loss or thermal insulation difference.
(5) Characters, graphics and other symbols shall not be printed on the welds used for welding and testing; The distance from the edge of the marking plate shall be greater than 0.5mm. In order to avoid printing material to dye the pad, cause various welding defects and affect the accuracy of testing.
(6) between welding plate, welding plate and access panel and welding plate and is greater than the welding plate width of interconnect or large area ground or shield connection of the copper foil, should have a thermal isolation, lead the line width should be equal to or less than half the width of welding plate (the smaller the solder shall prevail, generally width from 0.2 mm to 0.4 mm, and the length should be greater than 0.6 mm). If shielded by a solder mask, the width may be equal to the width of the solder plate (e.g. the connection to a large area of ground or shielded copper foil).
(7) for the same components, all symmetry using welding plate, such as chip resistor, capacitor, SOIC, QFP, etc.), the design should be strictly maintained its overall symmetry, the shape of the solder graphics are in complete accord with size (formed by the molten solder, welding area equal), and the position of the shape of the graphic should be completely symmetrical (including the location of the interconnect lines derived from the bonding pad; Interconnections may be made at will if shielded by solder mask. In order to ensure that the solder melt, acting on the components of all solder surface tension can maintain balance (that is, its resultant force is zero), in order to facilitate the formation of an ideal high quality solder joints.
(8) Where welding pads of components without external pins (such as sheet resistance, capacitance, adjustable potentiometer, adjustable capacitance, etc.) shall not have through holes between the pads (i.e., there shall be no through holes under the component body; If use welding film to block the dead can be excluded), in order to ensure the quality of cleaning.
(9) For components with multiple pins (such as SOIC, QFP, etc.), the short connection between pin pads is not allowed to be straight, and should be followed by short connection after adding interconnection lines from the pads (except if shielded by welding film) so as to avoid displacement or misidentification of bridge after welding. In addition, interconnection lines should be avoided as far as possible between their pads (especially pins with fine spacing); Interconnections between adjacent pads shall be shielded by an anti-welding film.
(10) For components with multiple pins, especially those with spacing of 0.65mm or below, the reference mark of bare copper (such as adding two symmetric optical positioning marks of bare copper on or near the welding plate graph) shall be added for optical calibration when precise SMT is applied.
(11) When the wave peak welding process is adopted, the through hole on the pin pad should be generally 0.05 ~ 0.3mm larger than the pin wire diameter, and the diameter of the pad should not be more than 3 times of the aperture. In addition, for IC, QFP device welding plate graphics, when necessary, can be added to the melt welding material to pull the role of the process of auxiliary welding plate, to avoid or reduce the occurrence of bridging phenomenon.
(12) The welding pad used for welding surface mount components (i.e., the welding spot) shall not be used as the detection point; Special test pads must be designed to avoid damage to components. To ensure the normal welding inspection and production debugging.
(13) Test pads should be arranged on the same side of the PCB whenever possible. This not only facilitates detection, but also greatly reduces the cost of detection (automated detection is even more so). In addition, the test solder pad should not only be coated with tin-lead alloy, but also its size, spacing and layout should match the requirements of the test equipment used.
(14) If the size given by the components is the maximum and minimum, the average size can be used as the reference for the design of the welding plate.
(15) In computer design, in order to ensure that the designed graphics can achieve the required accuracy, the size of the selected grid units must match with it; For the convenience of drawing, every figure should be placed on the grid points as far as possible. For components with multiple pins and fine spacing (such as QFP), 0.0254mm (i.e. 1miL) must be selected as the grid unit size when drawing the center spacing of their pads, and the origin of coordinates drawn should always be set at the first pin.
In conclusion, for components with multi-pin fine spacing, the overall cumulative error shall be controlled within ±0.0127mm (0.5mil) during the design of the solder pad.
(16) All kinds of welding pads designed shall be together with the carrier PCB. After passing the test welding and testing, they can be officially used for production. This is especially true for mass production.
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